1. Field of the Invention
This invention relates to the field of electronic solid state timepieces.
2. Prior Art
Electronic timepieces are well known which have a continuously operating clock and a chain of series connected counters. In the normal mode of operation, there is a lengthy sequence of pulses which progresses through the counters before the counters repeat themselves. For example, a solid state wristwatch may have a continuous clock operating for example, at 64 Hz which is applied to the first in a series chain of counters. The first counter in the chain may be a divide by 64 counter; the second a divide by 60 counter; the third a divide by 60 counter; and the fourth a divide by 12 counter. Accordingly, the output of the first through fourth counters provides respectively signals corresponding to parts of seconds, minutes, hours and days. In order to set these electronic timepieces, it has been known to independently return to zero at least some of the counters as generally set forth for example in U.S. Pat. No. 3,756,011.
Prior testing of timepieces and their counters after construction has left much to be desired. Testing has been particularly difficult when the counter and decoder driver circuitry of the timepiece is contained within a single complementary metal oxide semiconductor (CMOS) chip. The reason is that there is no commercially practical way to provide test points within the semiconductor chip and to reach the counters themselves. The only way that these counters may be reached is by having interconnecting wires at the edge of the chip and the package with these interconnecting wires serving no other purpose other than testing. This is unacceptable since the cost of such additional wiring would be prohibitive.
It is very desirable for proper testing techniques to reach each of the counters independently and particularly the hour and minute counters. These counters ordinarily make changes at such a low frequency rate with respect to the input clock that the actual time of test would be so long as to be commercially impractical.
It has been known to apply as a test frequency, a high frequency test clock. However, the value of the high frequency is limited by the operating limits of the input circuitry. Specifically, the first counter in the chain of counters may be a divide by 64 counter and it is that counter which is receiving the highest frequency and which limits the maximum value of the applied test frequency. Accordingly, even if a high permissible test frequency were used, it would still take a substantial amount of time to test the hour counter, for example.